1. Technical Field
The present disclosure pertains to a frequency synthesizer circuit and, more particularly, to a frequency synthesizer circuit having a phase locked loop circuit that reduces undesired spurious sidebands while maintaining phase noise performance.
2. Description of the Related Art
Frequency synthesizers may be employed in communication or entertainment applications such as in receivers for radio frequency tuners for receiving and tuning broadcasting signals. A frequency synthesizer of such system may include a phase locked loop (PLL) comprising a controlled oscillator, such as a voltage controlled oscillator, a loop filter, and a phase-frequency detector. Further, a frequency divider may be coupled to the controlled oscillator for dividing down the frequency of the controlled oscillator output signal. In such frequency divider, the frequency division may be adjusted in response to a control signal at the frequency divider which is indicative of a divisor value. The phase-frequency detector compares the phase and frequency of a periodic input or reference signal against the phase and frequency of the output signal of the frequency divider. The output of the phase-frequency detector is a measure of the phase and frequency difference between the two inputs. Control signals of the phase-frequency detector may be supplied to a charge pump that generates a control signal (e.g., a current signal) that is low-pass filtered by a loop filter and then provided to the controlled oscillator. The controlled oscillator usually generates the output signal of the PLL. This output signal can be used, for example, as controlled oscillator signal for a receiver mixer of a receiver chain in a tuner for radio frequency signals.
In one approach that has been used, the frequency divider divides the frequency of the controlled oscillator in response to a multi-bit divisor value, wherein a sigma-delta modulator is provided that varies at its output a division control signal over time such that the frequency of the controlled oscillator which is divided by the frequency divider may be adjusted according to a fractional divisor value over time.
In FIG. 1, there is shown a frequency synthesizer circuit according to one approach that has been used. The frequency synthesizer circuit 100 includes a phase locked loop circuit having a phase-frequency detector (PFD) 21, a charge pump 22, a loop filter 23, a voltage controlled oscillator (VCO) 24, and a frequency divider 60 implemented as an integer-divider 60 and which provides an output signal which is lower in frequency than the VCO output signal. The frequency divider 60 has a control input CTRL1 for adjusting the frequency division in response to a received control signal which is generated from a divisor value 37 provided as a multi-bit input signal having integer bits indicative of an integer part of a divisor value and having fractional bits indicative of a fractional part of the divisor value.
The phase-frequency detector 21 receives the divided VCO output signal from the divider 60 at one input terminal and compares the phase and frequency to a reference signal CKREF received at the other input terminal. Based on the comparison of these signals, the PFD 21 generates control signals to the charge pump 22, which generates a control signal (e.g., a current signal) that is low-pass filtered by the loop filter 23. The output signal of the loop filter 23 is provided to the VCO 24 which tunes the frequency of its output signal CKVCO accordingly. The output signal CKVCO is divided down by the frequency divider 60 which provides an output clock signal CKOUT1 divided down from an input clock signal CKIN provided by VCO 24. Further, a sigma-delta modulator 62 is provided which includes an input IN for receiving a multi-bit input signal which contains fractional bits of the divisor value 37 which is used for adjusting the division of the frequency divider 60. An output OUT of the sigma-delta modulator 62 is coupled to an adder 63 which also receives integer bits of the divisor value 37 and produces the control signal supplied to the frequency divider 60. Moreover, a dithering circuit 61 is provided which provides a dither signal coupled as a least significant bit (LSB) of the multi-bit input signal to the input IN of the sigma-delta modulator 62, as set out in more detail below. The circuits 61 and 62 each have a clock input CK for receiving a clock signal provided by the frequency divider 60.
Like any other type of phase locked loop, a sigma-delta PLL (SD-PLL, such as shown in FIG. 1) is a control loop which maintains a fixed phase relation between an external reference clock and an internal generated clock. Due to its loop gain it can be used, in analogy to a non-inverting amplifier, to “amplify” the frequency of a clock source. In other words, it can generate clock frequencies at multiples of an external reference clock frequency.
A digital sigma-delta modulator (SDM) is used in a SD-PLL to control an integer feedback divider such as integer-divider 60 as shown in FIG. 1, in order to obtain not only integer but also fractional multiples of the external reference clock frequency. Hence, a sigma-delta PLL is a so-called fractional-N frequency synthesizer.
With a constant or periodic input signal, a digital sigma-delta modulator is a periodic system, i.e., the re-occurrence of its internal states shows a certain periodicity. Hence, the quantization noise which is added to the input signal by the SDM is as well periodic and, therefore, in reality the so-called quantization noise is not a random, but instead a deterministic signal. The dominant ones of the discrete tones, the spectra of any periodic signal consists of, are called idle tones in case of sigma-delta quantization noise. These idle tones are present as undesired spurious sidebands at the VCO output in a sigma-delta PLL. In FIG. 2, there is shown a signal diagram showing the spectra of an exemplary sigma-delta quantization noise at the VCO output in a sigma-delta PLL in which the idle tones, which are present as undesired spurious sidebands, are shown as peaks on the left and right sides of the spectrum. A quantization noise such as shown in FIG. 2 may be present in a sigma-delta PLL such as shown in FIG. 1 with a divider fractionality 0.012, a reference frequency Fref=36.5 MHz of the reference clock signal CKREF, with 10% charge pump current mismatch and dithering of the LSB of the input signal of the sigma-delta modulator as shown in FIG. 1.
To reduce the total power of all idle tones, it is desirable to maximize the period of the quantization noise signal, which is also called limit cycle. While this is sufficient if the quantization noise is subject to strictly linear signal processing, it is not sufficient in case of non-linear signal processing. Quantization noise which appears to be free of idle tones in a linear system can exhibit significant idle tones in a non-linear system.
As existing PLLs in practice always contain weakly non-linear building blocks, e.g., a single-ended charge pump with inevitable up-/down current mismatch, there is a second requirement to the quantization noise, namely that it must be tolerant to non-linear distortion regarding idle tones.
To increase the limit cycle in conventional sigma-delta PLLs, there is often at the least significant bit (LSB) of the sigma-delta modulator a dither signal injected (e.g., from a linear feedback shift register—LFSR), such as shown in FIG. 1. In this way, the output of the sigma-delta modulator is dithered to change in a pseudo-random fashion so that the power of the noise generated by the sigma-delta-modulator is spread over a frequency band, thereby reducing the power of the noise at a particular frequency. Another strategy of maximizing limit cycles is to set certain initial values in the accumulators of the sigma-delta modulator in such a way that the modulator is forced to loop in the longest possible sequence of unique internal states for any given static input signal. Although good results can be achieved with these methods in idealized simulations with solely linear PLL building blocks, in real-world PLLs their effectiveness is very limited due to insufficient tolerance of the quantization noise to non-linear distortion. This is true for both single loop and cascaded modulators, even if cascaded modulators tend to be more tolerant at the expense of higher quantization noise.